The strategic logic of China's AI compute programme is not subtle. Faced with restricted access to the most advanced accelerators, Chinese engineers stopped optimising the single chip and started optimising the system.
The result is the supernode: hundreds or thousands of accelerators tightly coupled into something that behaves like one machine.
Key takeaways
- System over chip: Huawei's CloudMatrix 384 / Ascend 384 supernode integrates 384 Ascend 910C accelerators, delivering roughly 300 PFLOPS of BF16 dense compute — vendor figures place it at about 2x an NVIDIA GB200 NVL72 with roughly 3.6x the total memory.
- Deployed at scale: more than 500 sets had been deployed nationwide by the first half of 2026, with vendor-cited commercial deployments above 750 sets. Reported training speed-ups: 2.5x+ for dense hundred-billion-parameter models and up to 3x for MoE models.
- A 10,000-card milestone: in July 2026, the first "domestic chips training domestic models" Ascend 10,000-card cluster in the Greater Bay Area went live in Shaoguan, Guangdong — 30 supernodes, 11,520 cards, 9,000P of total compute.
- Next generation: the Ascend 950 supernode made its first physical appearance at WAIC 2026. The Atlas 950 SuperCluster is designed to scale to 500,000 cards with a 256 TB shared high-speed memory pool; the SuperPoD supports up to 8,192 Ascend 950DT cards at 1 EFLOPS FP8, with batch availability planned for Q4 2026.
- Share: Huawei Ascend shipped about 812,000 accelerator cards in 2025 — roughly 49% of the domestic market and nearly half of all domestically produced AI accelerators. Domestic AI chip shipments overall passed 40% of the market, reaching about 1.65 million cards.
Why supernodes are the right answer
Modern AI training is limited by three walls: memory per chip, communication bandwidth between chips, and power. If a single chip cannot be made bigger, the alternative is to make many chips behave like one — which is fundamentally a networking problem.
China has world-class networking and systems-integration capacity. Treating the cluster as the unit of compute plays to that strength. It is, in effect, the same insight that made Chinese manufacturing competitive: if you cannot win on the most advanced component, win on integration and scale.
The approach has been validated by the models themselves. The Ascend 384 supernode has completed adaptation for major models from Zhipu AI, the Beijing Academy of Artificial Intelligence and DeepSeek; Zhipu is reported to have trained GLM-5.1 end-to-end on more than 100,000 Ascend cards.
The product cadence
Huawei's roadmap has been described as one generation per year with compute roughly doubling:
- Ascend 910C — current volume workhorse, manufactured on SMIC's N+2 process, 128 GB HBM, 780 TFLOPS FP16, positioned against the H800 class.
- Ascend 950PR — inference-oriented card launched Q1 2026, 128 GB memory and 1.6 TB/s bandwidth, reported at roughly 2.87x the inference performance of an H20.
- Ascend 950DT — training card planned for Q4 2026, 144 GB of proprietary HiZQ 2.0 memory at 4 TB/s, aimed at trillion-parameter MoE training.
Annual output targets for the Ascend family in 2026 have been reported in the range of 1.5 to 2 million cards, which would hold roughly half of China's domestic AI accelerator market.
The software question
Hardware without a software stack is a space heater. This was the most-cited weakness of Chinese AI silicon, and it is where 2026 saw the most consequential moves:
- CANN, the Ascend compute architecture, has been fully open-sourced, with an ecosystem reported at over 3,000 partners.
- DeepSeek V4 shipped with Day-0 adaptation across nine domestic AI chips — the clearest signal that China's model layer and silicon layer are now being developed together.
- GLM-5.3-Flash is reported to be serving production traffic on domestic clusters at per-token cost comparable to mainstream NVIDIA GPUs.
The real bottlenecks
The constraints are now manufacturing, not design. Analysts identify three: wafer fabrication, HBM memory, and advanced packaging. Ascend 950 production, for instance, is reported to be limited to roughly 8,000–9,000 units per month by HBM and 2.5D packaging capacity — which is why the highest-end parts are allocated first to large internet companies and national supercomputing centres.
The consensus expectation is that these constraints begin easing from 2027 as domestic HBM3 ramps and advanced packaging and leading-edge capacity expand. Until then, China's compute story is a story of systems engineering against a supply ceiling — and, for now, it is working.
Figures from company disclosures, securities research and Chinese industry media reporting in 2026. Vendor performance comparisons are vendor-claimed unless otherwise noted.